Mirror Full Adder IC Layout in Cadence Virtuoso

I designed a 28-transistor mirror full adder in Cadence Virtuoso. I began by taking the truth table and producing logic expressions. After extracting a simplified expression for the Sum and Carry outputs I was able to produce the associated CMOS schematic. Once the schematic was drawn, simulated, and verified I determined the associated Euler path. From the Euler path I derived the stick diagram used to create my layout.

After laying out the full adder, I performed various simulations to verify my design. The simulations proved that my design would operate with a junction temperature up to ~50°C at a 160MHz input frequency.

You can view the full report as a PDF here.

Here is my full report:

The following information can be used to help produce the design of the 28 transistor mirror full adder circuit:

full_adder_truth_table

The boolean expressions for Sum and Cout can be obtained by putting the truth table into a program called “Espresso” which performs a sort of automated Karnaugh map solution.

Input File

Output File

# Adder Input

.i 3

.o 2

000 00

001 10

010 10

011 01

100 10

101 01

110 01

111 11

# Adder Output

.i 3

.o 2

.p 7

100 10

010 10

001 10

111 10

-11 01

1-1 01

11- 01

.e

The expressions can then be obtained by performing a SoP on the output. This yeilds:

Sum=A\overline{BC}+\overline{A}B\overline{C}+\overline{AB}C+ABC=A\oplus B\oplus C

C_{out}=BC+AC+AB=AB+C(A+B)

The expression for Sum can be further reduced by the following logical simplifications:

Sum=(A+B+C)\overline{(BC+AC+AB)}+ABC=(A+B+C)\overline{C}_{out}+ABC

Since it is desirable to have the boolean expressions represent the pull-up structure of the circuit, which consists of pfets that typically require low inputs in order to drive the output high, the form of the outputs must therefore be inverted in order to reflect the desired structure. This yields:

\bf{\overline{Sum}=\overline{(A+B+C)\overline{C}_{out}+ABC}}

\bf{\overline{C}_{out}=\overline{AB+C(A+B)}}

These directly correspond to the pull-up structure of the circuit and the outputs merely need to be inverted in order to get their desired results. Using graph theory techniques or other methods will convey that the dual structure exactly mirrors the established pull-up. Resulting in a schematic (whose logic can be tested using something like Logisim) such as the following:

schematic

The width-to-length ratios are determined by ensuring that the worst case (when a maximum of one transistor at a parallel site is on) for both the pull-up and pull-down paths have equivalent dimensional ratios to the associated reference inverter. The ratio of the carrier mobilities is the factor that is used between the two dimensions in order to keep the propagation time from low to high and from high to low equal (~2.7 is typically used for silicon wafers)

(\frac{W}{L})_p=\frac{\mu_n}{\mu_p}(\frac{W}{L})_n\cong2.7(\frac{W}{L})_n

The reference inverter that was selected consisted of an nfet whose W/L=10 and a pfet whose W/L=2.7×10=27. Since Cadance places an upper limit of 54μm on the width of any transistor whose length is less than 1.2μm in length, in order to keep the lengths of each transistor in the circuit uniform and still match the reference inverter, the selected length must be greater than 1.2μm (here 1.5μm was selected for numerical simplicity). All widths were adjusted in order to ensure the worst case paths matched the reference. The critical path, which is the path between Cin and Cout, is the path which one might cascade several of these adders together. Therefore, increasing the widths of the transistors along this path may be advantageous.

Schematic

cadence_schematic

Symbol Schematic

symbol_schematic

The colors on the nodes of this schematic correlate directly with each of the preceding plots.

Plot

plot

This completely agrees with the truth table. Cin has the highest frequency and its period is 20ns here.

Layout passing DRC

layout_passing_drc

Extracted Layout Passing LVS

extracted_layout_passing_drc

Each of the following plots have had their frequencies ramped up in order to better see the effects, Cin’s period is now 6ns.

Parasitics Output Speed Comparison (Pink is Sum, Blue is Cout)

paracitics_output_speed_comparison

The plot with ∇ is the Sum output with parasitics and the ∆ is the Cout with parasitics (they contain more “spikes”).

Temperature Effects on Output Speeds (Without Wire Paracitics)

@ -75°C, 27°C, 200°C (Pink is Sum, Blue is Cout)

temperature_effects_on_output_speeds

Temperature Effects on Output Speeds (With Wire Paracitics)

@ -75°C, 27°C, 200°C (Pink is Sum, Blue is Cout)

temperature_and_para_effects

The transient effects are quite obvious in these plots.

Click-Clock Board

The Click-Clock Board is a digital 7-segment display clock I developed using KiCad, Verilog, MyHDL, Logisim, Icarus Verilog, GTKWave, Espresso, a solderless breadboard, and a Spartan 6-based FPGA board called Mojo V3.

The first PCB prototype was hand soldered by me using 0.5mm diameter lead-free solder. I am planning to reflow the next board using solder paste for much nicer assembly.

click-clock-board

Figure 1: Click-Clock Board Layout (v0.2)

IMG_20170409_185623

Figure 2: Front of the First Prototype (v0.1)

IMG_20170408_160053

Figure 3: Back of the First Prototype (v0.1)

bread_board

Figure 4: Complete and Working Breadboard Proof-of-Concept of the Click-Clock Board

clock_color

Figure 5: Working Logisim Simulation of the Click-Clock Board

seconds

Figure 6: GTKWave Seconds Waveform of the Click-Clock Board’s Verilog Simulation

minutes

Figure 7: GTKWave Minutes Waveform of the Click-Clock Board’s Verilog SImulation

hours

Figure 8: GTKWave Hours Waveform of the Click-Clock Board’s Verilog Simulation

LulzBot Automatic Tool Head Changing System

We developed a system which will allow our upcoming 3D printers to change their tool heads during a print. Thus far, we have produce two successful prototypes. It uses the OpenGrab electropermanent magnet for the attachment mechanism.

The tool head PCB has a MAX31855 for thermocouple measurement, 25AA02UIDT EEPROM for storing calibration data, pass-through traces for switching loads, and a spot for a quadrature rotary encoder to sense filament movement.

The project’s Git repo can be found here.

Here’s a video helping to visualize the magnetic field produce by the electropermanent magnet with the use of ferrofluid. Specifically, when the net external magnetic field is zero, when the AlNiCo is saturated with all moments aligned and the net external magnetic field is non-zero, while being gaussed, and while being de-gaussed:

Here’s a demo video of our first print while keeping the toolheads heated in the docking station:

Here’s a demo video our first prototype during a print:

Here’s the layout of the tool head PCB I designed in KiCad:

tool-head-pcb

Figure 1: Tool Head PCB Layout

Here’s the schematic:

Screenshot from 2017-03-12 22-02-28

Figure 2: Tool Head PCB Schematic

Here’s the carriage connector PCB with spring-loaded connectors (don’t worry, the traces aren’t being masked/exposed):

carriage-pcb

Figure 3: Carriage Connector PCB Layout

Here’s a photo showing the tool head PCB in use during a print:

IMG_20170308_162713

Figure4: The Tool Head PCB in Action

The main electronics on this machine is the Replicape rev B3A (Trinamic TMC2100) and BeagleBone Black rev C using the TI AM3358 1GHz 32-bit ARM Cortex A8 and 512MB DDR3 as seen in Figure 5. The OS being Debian, running the Redeem Linux daemon, and an OctoPrint web server.

IMG_20170310_160726

Figure 5: Main Electronics

LulzBot Mini Research and Development

The LulzBot Mini has recently (November 15, 2016) had a huge overhaul with the introduction of Mini v1.04 (codenamed Gladiola). The changes made needed to be subtle enough whereas a SKU change did not have to be made, making the improvements even more challenging to pull off.

The requirements for the electrical system in this release were the following:

  • Use completely new and custom cabling which can handle continuous flexing and outlast the printers’ lifetime (praised by users)
  • Significantly reduce the complexity of installation and assembly for the electronics and wiring; increase rate of production (manufacturing’s assembly instructions)
  • Eliminate an extreme falure mode which would destroy the MCU when the contents of the hotend’s heating element is shorted to its housing
  • Increase the EMC repeatability of the machines; Introduce proper grounding, masking, shielding, filtering, and low impedance return path schemes (test report, more docs)
  • Overall reduction in electronics related RMAs
  • Use the latest revision of Ultimachine’s Mini-RAMBo (with more unintentional radiating antennas)

The EMC improvements made could only be done at the machine/wiring level due to the electronics having been designed in proprietary software. Several Gladiola machines were tested and passed Class B, significantly increasing our sample size. Without proper grounding, shielding, and filtering the PCB could produce quasi-peaks which are as much as 10dB above the Class A limit. The radiated emissions were also found to be lower than several competitors.

mini_before_after
Figure 1: Electronics enclosure before (v1.03 and earlier) and after (v1.04)
mini_chamber

Figure 2: LulzBot Mini v1.04 (3 Meter) Test Setup for Radiated Emissions

The requirements for the firmware in this release were the following:

  • Base the release off of upstream Marlin 1.1.0
  • Eliminate an extreme failure mode which causes the toolhead to crash into to the bed when probing fails (praised by users, commit, see Figure 3)
  • Measurably improve the extruder fan consistency during operation; the solution was modifying the PWM frequency by changing AVR register values (commit)
  • Create an additional branch which allows for a GLCD controller to be used
  • Account for dimensional changes between v1.03 (and earlier) and 1.04, backwards compatibility with all previous Minis
  • Add proper thermal runaway protection (commits: 247f680ef509d957f9543734)
  • Eliminate several bugs present in upstream (such as serial ring buffer overflow)
  • Create pull requests and have them merged upstream for all significant bug fixes and improvements to the firmware (commits merged upstream)
  • Create a makefile which can be used to build the firmware
  • Create a manufacturing firmware checksum script and procedure
LulzBot-Mini-PEI-bed-damage

Figure 3: Failure Mode Prevented by Second Bullet Point

GLCD Development

In addition to each of these improvements, I also re-drew the GLCD board in KiCad with improved routing, proper grounding, and ESD protection (project files).

glcd

Figure 4: GLCD KiCad Layout and 3D Rendering in FreeCAD

IMG_20170316_133416

Figure 5: Back of the GLCD PCB

IMG_20170316_133407

Figure 6: Front of the GLCD PCB

IMG_20170317_075144

Figure 7: Custom GLCD Controller on a Mini

LulzBot TAZ 6 Research and Development

The LulzBot TAZ 6 was officially released May 17, 2016. There have been many improvements to the quality, reliability, and performance. The electrical system experienced a massive overhaul compared to the TAZ 5.

The requirements for the electrical system in the TAZ 6 were the following:

  • Repeatably pass FCC and CE Class B radiated emissions as well as compliance with all other EMC standards; Introduce proper grounding, masking, shielding, filtering, and low impedance return path schemes (test report)
  • Significantly reduce the complexity of installation and assembly for the electronics and wiring; increase rate of production (manufacturing’s assembly documentation)
  • Introduce ESD protection and significant immunity to ESD events
  • Endstops are normally-closed to reduce EMI and to account for open-circuit failure modes

The EMC improvements made could only be done at the machine/wiring level due to the electronics having been designed in proprietary software. Several TAZ 6 machines were tested and passed Class B, significantly increasing our sample size. On the TAZ 5 which lacks proper grounding, shielding, and filtering the PCB transmits quasi-peaks which are ~7dB above the Class B limit.

TAZ_6_controlbox_front_open

Figure 1: TAZ 6 Electrical Enclosure

IMG_0480_2.JPG.400x300_q85_crop_upscale

Figure 2: TAZ 5’s Crammed, Messy Electrical Enclosure

taz_chamber

Figure 3: LulzBot TAZ 6 (3 Meter) Test Setup for Radiated Emissions

Here is a video of a customer describing the EMC mitigation efforts:

The requirements for the firmware in the TAZ 6 were the following:

  • Base the release off of upstream Marlin 1.0.2
  • Add proper thermal runaway protection (commits: 94308924490ed460d8461a9f,  18f22da21171073934caae06,  106d928ad9bb)
  • New feature to allow the user to adjust the Z-Offset from the GLCD in real-time during the print and store the value to the MCU’s EEPROM when done (see Figure 4)
  • Eliminate several bugs present in upstream
  • Create pull requests and have them merged upstream for all significant bug fixes and improvements to the firmware (commits merged upstream)
  • Create a makefile which can be used to build the firmware
  • Create a manufacturing firmware checksum script and procedure
IMG_2663.JPG.600x0_q85

Figure 4: Adjusting the Z-Offset From the GLCD with Animations

3D Platform – Improvements

Resuming A Really Long Print

If you have ever ran a 3D print that lasts a week or longer the last thing you want is to lose hundreds of dollars in material due to a power outage or some other unforeseen problem. I wrote a special feature for 3D Platform in order to be able to complete one of these extremely long prints when such an event occurs.

Here is a video demonstrating the feature in action:

The way it works is the given Z coordinate when selecting “Resume SD from Z” is used to truncate all movements, including retraction Z-hops, which are evaluated to be less than the given value. The result is a perfectly completed print with no noticable recovery artifacts.

3DP1000 Electrical Panel

I developed a modular electrical panel and enclosure for the CE compliant 3DP1000.

Workbench Series Android Tablet Interface

I developed a platform which had an Android tablet running a chroot Fedora GNU/Linux environment, hosting a VNC server for remote access, along with a custom tablet interface of Pronterface.

IMG_20150917_101250

Workbench Series Electrical Panel

I developed the electrical system with a drawer style panel for the 3DP Workbench.