Mirror Full Adder IC Layout in Cadence Virtuoso

I designed a 28-transistor mirror full adder in Cadence Virtuoso. I began by taking the truth table and producing logic expressions. After extracting a simplified expression for the Sum and Carry outputs I was able to produce the associated CMOS schematic. Once the schematic was drawn, simulated, and verified I determined the associated Euler path. From the Euler path I derived the stick diagram used to create my layout.

After laying out the full adder, I performed various simulations to verify my design. The simulations proved that my design would operate with a junction temperature up to ~50°C at a 160MHz input frequency.

You can view the full report as a PDF here.

Here is my full report:

The following information can be used to help produce the design of the 28 transistor mirror full adder circuit:

full_adder_truth_table

The boolean expressions for Sum and C_out can be obtained by putting the truth table into a program called “Espresso” which performs a sort of automated Karnaugh map solution.

Input File

Output File

# Adder Input

.i 3

.o 2

000 00

001 10

010 10

011 01

100 10

101 01

110 01

111 11

# Adder Output

.i 3

.o 2

.p 7

100 10

010 10

001 10

111 10

-11 01

1-1 01

11- 01

The expressions can then be obtained by performing a SoP on the output. This yeilds:

$Sum=A\overline{BC}+\overline{A}B\overline{C}+\overline{AB}C+ABC=A\oplus B\oplus C$

$C_{out}=BC+AC+AB=AB+C(A+B)$

The expression for Sum can be further reduced by the following logical simplifications:

$Sum=(A+B+C)\overline{(BC+AC+AB)}+ABC=(A+B+C)\overline{C}_{out}+ABC$

Since it is desirable to have the boolean expressions represent the pull-up structure of the circuit, which consists of pfets that typically require low inputs in order to drive the output high, the form of the outputs must therefore be inverted in order to reflect the desired structure. This yields:

$\bf{\overline{Sum}=\overline{(A+B+C)\overline{C}_{out}+ABC}}$

$\bf{\overline{C}_{out}=\overline{AB+C(A+B)}}$

These directly correspond to the pull-up structure of the circuit and the outputs merely need to be inverted in order to get their desired results. Using graph theory techniques or other methods will convey that the dual structure exactly mirrors the established pull-up. Resulting in a schematic (whose logic can be tested using something like Logisim) such as the following:

schematic

The width-to-length ratios are determined by ensuring that the worst case (when a maximum of one transistor at a parallel site is on) for both the pull-up and pull-down paths have equivalent dimensional ratios to the associated reference inverter. The ratio of the carrier mobilities is the factor that is used between the two dimensions in order to keep the propagation time from low to high and from high to low equal (~2.7 is typically used for silicon wafers)

$(\frac{W}{L})_p=\frac{\mu_n}{\mu_p}(\frac{W}{L})_n\cong2.7(\frac{W}{L})_n$

The reference inverter that was selected consisted of an nfet whose W/L=10 and a pfet whose W/L=2.7×10=27. Since Cadance places an upper limit of 54μm on the width of any transistor whose length is less than 1.2μm in length, in order to keep the lengths of each transistor in the circuit uniform and still match the reference inverter, the selected length must be greater than 1.2μm (here 1.5μm was selected for numerical simplicity). All widths were adjusted in order to ensure the worst case paths matched the reference. The critical path, which is the path between Cin and Cout, is the path which one might cascade several of these adders together. Therefore, increasing the widths of the transistors along this path may be advantageous.

Schematic

cadence_schematic